Evolvable Hardware for Generalized Neural Networks

This paper describes an evolvable hardware (EHW) system for generalized neural network learning. We have developed an ASIC VLSI chip, which is a building block to configure a scalable neural network hardware system. In our system, both the topology and the hidden layer node functions of a neural network mapped on the chips are dynamically changed using a genetic algorithm. Thus, the most desirable network topology and choice of node function (e.g. Gaussian or sigmoid) for a given application can be determined adaptively. This approach is particularly suited to applications requiring ability to cope with time-varying problems and real-time timing constraints. The chip consists of 15 Digital Signal Processors (DSPs), whose functions and interconnections are reconfigured dynamically according to the chromosomes of the genetic algorithm. Incorporation of local learning hardware increases the learning speed significantly. Simulation results on adaptive equalization in digital mobile communication are also given. Our system is two orders of magnitude faster than a Sun SS20 on the corresponding problem. 1 Introduction The traditional applications of neural networks focused on the off-line learning of a given function using a single network whose weights are gradually modified. In recent years, the alternative approach of on-line adapting by reshaping the network itself has been attracting renewed attention [Fiesler, 1994]. The on-line approach has the advantages of efficiency and flexibility which are impossible with the off-line approach. We embody this on-line approach with evolvable hardware (EHW) [Higuchi et al., 1992][Higuchi et al., 1994]. Ability of this method to dynamically adapt to changing situations is particularly suited to practical industrial applications. However, optimal performance for a given application is produced by an architecture with the most suitable topology and the most appropriate node functions (i.e. sigmoid or Gaussian). Further, to meet the time constraints imposed by real-time applications, neural network hardware systems need to be 'tailored' to the size of the ideal network for the problem. In general, it is very difficult to design an optimal neural network and process it with scalable parallel hardware. To solve these two problems, we have developed (1) a learning scheme which utilizes genetic algorithms (GAs) to automatically select both the optimal network topol-ogy and the node functions, and (2) an evolvable hardware chip that functions as a building block for configuring a scalable neural network. A concept of EHW is an innovative hardware design methodology for truly adaptive hardware systems [Higuchi, 1997]. In systems …